201720162015
1Title: Nanoelectrode Technologies for the Brain
Speaker:
Dr. Krishna Jayant, Columbia University, New York, NY
Date & Venue: 24-07-2017, Girish Gaitonde conference room, Girish Gaitonde bldg., 2nd floor, EE Dept., IIT Bombay- 400076.
Abstract: Dr. Jayant talked about the quantum-dot labeled quartz nanopipettes (15-30 nm inner diameters) which under two-photon visualization enables targeted intracellular recordings from spines, and also explained a new method termed "SPEER" (Sharp and Prism Enabled Electrophysiological Recordings), which enables high-throughput targeted intracellular electrophysiology in vivo using flexible nanopipettes. How the interdisciplinary approach of combining nanoelectronics, microfabrication, and state-of-the-art multi-photon microscopy can help decipher the biophysical substrate underlying single neuron computation and overall microcircuit function was also discussed.
2Title: Nanomaterials for optoelectronic applications
Speaker:
Dr. Amitha Shetty, JNCASR, Bangalore
Date & Venue: 11-07-2017, Girish Gaitonde conference room, Girish Gaitonde bldg., 2nd floor, EE Dept., IIT Bombay- 400076.
Abstract: The talk was based on the fabrication of a free-standing inorganic/organic hybrid structures of ZnO nanostructures with a conducting polymer,PEDOT:PSS, which performs as photodetectors. Dr. Shetty discussed about the synthetic technique which demonstrates how the thermodynamics of a material can be effectively used to obtain DMS (dilute magnetic semiconductors) quantum dots with varying transition metal ions which shows superior magnetic and optical properties.
3Title: 3D Monolithic Integration for advanced CMOS and towards Neuromorphic Systems
Speaker:
Dr. Veeresh Deshpande, IBM -Zurich Research Laboratory
Date & Venue: 06-07-2017, Nanoelectronics conference room. EE Annex Bldg., 3rd floor, EE Dept., IIT Bombay- 400076.
Abstract: Advanced CMOS technology with 2D planar integration of devices is facing serious challenges in terms of area scaling due to lithographic limitations. 3D monolithic (3DM) integration has the potential to achieve very high circuit densities without device scaling, due to high granularity provided by transistor level stacking. The talk was focused on the III-V device integration and 3D CMOS circuits utilized as test-vehicles to demonstrate the 3D monolithic platform.
4Title: Packaging without the Package – A More Holistic Moore’s Law (IEEE AP/ED Bombay Chapter - Distinguished Lectures)
Speaker:
Prof. Subramanian Iyer, FIEEE*, UCLA, USA
Date & Venue: 23-05-2017, Girish Gaitonde conference room, Girish Gaitonde bldg., 2nd floor, EE Dept., IIT Bombay- 400076.
Abstract: Silicon features have scaled by over 1500X for over six decades, and with the adoption of innovative materials delivered better power-performance, density and till recently, cost per function, almost every generation. This has spawned a vibrant system-on-chip (SoC) approach, where progressively more function has been integrated on a single die. Novel methods of system integration, heterogeneous integration the backbone of a new SoC methodology, and the concepts to flexible and biocompatible electronics with medical engineering applications were the topics discussed during this talk.
5Title: Power Management Solutions Enabled by Mixed-Signal Technologies and Intelligence (IEEE AP/ED Bombay Chapter - Distinguished Lectures)
Speaker:
Dr. Bin Zhao, FIEEE*, ON Semiconductor, USA
Date & Venue: 19-05-2017, Girish Gaitonde conference room, Girish Gaitonde bldg., 2nd floor, EE Dept., IIT Bombay- 400076.
Abstract: Many electronic products are essential in our daily life, which include not only the PCs with microprocessors and memory chips but also the wireless/mobile communication devices, portable multimedia devices, large-scale/high-definition displays, various entertainment systems, home appliances, healthcare wearable devices, smart sensing and IoT. Dr Zhao discussed the challenges in power management and the innovative solutions enabled by mixed-signal design and technologies for the advantages in performance, power efficiency, and cost during this talk.
6Title: All-Carbon Interconnects – From 1D to 3D (IEEE AP/ED Bombay Chapter - Distinguished Lectures)
Speaker:
Prof. Cary Yang, FIEEE*, Santa Clara University, USA.
Date & Venue: 18-05-2017, Girish Gaitonde conference room, Girish Gaitonde bldg., 2nd floor, EE Dept., IIT Bombay- 400076.
Abstract: Continuous downward scaling in silicon integrated circuit technology into the sub-20 nm regime has created critical challenges in chip manufacturing, among them, reliability and performance of on-chip interconnects. The feasibility of fabricating a 3D CNT/graphene device, which can serve as the building block for all-carbon interconnects, was the topic of discussion. Enhanced understanding of the relationship between interfacial nanostructure and device resistance can lead to eventual functionalization of contacts between CNT vias and a graphene-based planar interconnect network in the most advanced technology nodes, were also discussed.
7Title: Power Electronics for 21st Century Energy Economy (IEEE AP/ED talk)
Speaker:
Dr.Krishna Shenai,NMAM Institute of Technology, Nitte, Karnataka
Date & Venue: 17-03-2017, Girish Gaitonde conference room, Girish Gaitonde bldg., 2nd floor, EE Dept., IIT Bombay- 400076.
Abstract: Power Semiconductor Switch Module (PSSM), briefly termed as Power Module (PM), forms the heart of a modern electrical power system much like the microprocessor in a computing or communication system . The power system constitutes as the building block of 21st century energy economy much like the computing and communication systems were for the 20th century information economy. Imminent opportunities and challenges that exist in India in both silicon and wide bandgap (WBG) power electronics including Gallium Nitride (GaN) and Silicon Carbide (SiC) materials were the key topics discussed during this talk.
8Title: IMS Bordeaux: Wave-based resonant microsensors for (bio) chemical detection, environmental and health related applications (IEEE AP/ED Bombay Chapter – Seminar Talk)
Speaker:
Prof. Corinne Dejous, IMS Bordeaux
Date & Venue: 02-03-2017, EEG-302 Seminar room, Girish Gaitonde bldg., 3rd floor, EE Dept., IIT Bombay- 400076.
Abstract: The talk focused on the Surface Acoustic Wave or SAW-based devices for highly sensitive and real-time chemical or biochemical sensing applications. This was followed by an overview showcasing the versatile effort made at IMS Bordeaux labs through a large spectrum of applications investigated, among them mainly environmental and health related ones. The materials are based on organic, inorganic, hybrid materials, either natural or engineered, typically with micro- to nano-structuration and surface modification for increased sensitivity and specificity.
9Title: Spin caloritronics in ordered alloy materials ( IEEE AP/ED Bombay Chapter Talk)
Speaker:
Prof. Masaki Mizuguchi, Tohoku University, Japan
Date & Venue: 21-02-2017, Nanoelectronics conference room. EE Annex Bldg., 3rd floor, EE Dept., IIT Bombay- 400076.
Abstract: The correlation between spin and charge in electronic transports has been energetically studied in a scheme of spintronics research. Recently, the coupling between heat current, spin current and charge current is also attracting much attention, and this newly established field is called “spin caloritronics”. During this talk Prof. Mizuguchi explained about the study on the correlation between magnetic anisotropy and the ANE in various materials. The enhancement effect of ANE with spin-wave spin currents in nanostructures was also discussed with theoretical viewpoints.
10Title: MEMS VOC Sensors, Patternable Piezoelectrics and Advances in Understanding of Energy Loss Mechanisms in MEMS Resonators
Speaker:
Dr. Saurabh Chandorkar, Stanford University and Consultant, IIT Bombay
Date & Venue: 12-01-2017, EEG-302 Seminar room, Girish Gaitonde bldg., 3rd floor, EE Dept., IIT Bombay- 400076.
Abstract: The talk was the about development of MEMS piezoeresistivecantilever based Volatile Organic Compound (VOC) sensor in IIT Bombay. This talk mainly focused on the activities in past 6 months and future directions for these kinds of sensors and also on the design optimization within the constraints of use of existing masks and future developments using topology optimization. Dr. Chandorkar also talked about the new research in understanding thermoelastic dissipation, temperature dependence of various energy loss mechanisms and topology optimization.
11Title: Mimicking Natural Ways of Computing in Solid-State Systems
Speaker:
Suman Datta, University of Notre Dame
Date & Venue: 10-01-2017, Nanoelectronics conference room. EE Annex Bldg., 3rd floor, EE Dept., IIT Bombay- 400076.
Abstract: In this talk experimental testbed comprising of compact coupled relaxation oscillator based dynamical system that exploits the insulator-metal transition in correlated oxide for example VO2), to efficiently solve the vertex coloring of arbitrary graphs, a prototypical combinatorial optimization problem was discussed. Dr. Datta also discussed that, the work is not only elucidates a physics-based computing method but also presents opportunities for building customized analog co-processors for solving computationally hard problems efficiently.
12Title: Acceleration of Power System Dynamics (Transient Stability) Simulation
Speaker:
Shrirang Abhyankar, Argonne National Laboratory, USA
Date & Venue: 09-01-2017, EEG-303, Seminar room, Girish Gaitonde bldg., 3rd floor, EE Dept., IIT Bombay- 400076.
Abstract: Speaker discussed about the research groups efforts on accelerating dynamics (transient stability) simulation of very large-scale power grids .He also covered, basics on high-performance computing for power system analysis during this talk followed by presentation on an introduction to the open-source numerical library 'Portable Extensible toolkit for Scientific Computing (PETSc).
13Title: Conjugated Polymers in Active Devices: Photovoltaics, Electrochromism and Charge Storage as Case Studies
Speaker:
John R. Reynolds, Georgia Institute of Technology, Atlanta, GA
Date & Venue: 04-01-2017, Girish Gaitonde conference room, Girish Gaitonde bldg., 2nd floor, EE Dept., IIT Bombay- 400076.
Abstract: Conjugated polymers provide a unique encompassing set of structurally tunable optical, electronic transport, and redox properties that allows their present and potential use in a host of applications which span, field effect transistors, light emitting diodes, electrochromism, solar cells, and photodetectors, along with batteries and supercapacitor. The talk focused on the synthesis and optimization of the morphology of solution processed π-conjugated oligomers and polymers, as they are applied in organic electronic devices.